1. Technical Field
The invention relates to power circuits, and particularly, to via structures in smart-power circuits.
2. Background Information
Current semiconductor device technology typically provides semiconductor substrates comprising multiple layers for device formation. In order that the necessary number of devices can be incorporated within a reasonably sized semiconductor substrate, and in order to provide for the required external connections, it is common to provide these multiple layers within the semiconductor device which allow for a multi-layered structure. Such a multi-layered architecture of devices will clearly improve the density of devices for a given area, and allow for more complex and powerful circuitry and devices to be provided.
Within multiple layered devices, it is necessary for connections to be made between certain given layers within the structures. Such connections are generally provided by metallic vias, which extend between given layers of the multi-layered structure. Such vias allow for electrical connection between vertically aligned layers, either for providing signals or power or the like, to each of the layers and devices held therein.
Typically, vias are designed as squares in cross-section, which extend between the chosen layers of the multi-layer substrate. While such vias are convenient and appropriate for low power devices, or signal transfer, more significant difficulties are encountered when applied to power devices. The use of higher power in multi-layer devices, requires that the via structures carry increased currents. Increased currents through small metallic vias, will lead to higher resistance effects and resistive heating thereof. In many applications, such effects can be significant and actually degrade performance of the multi-layer structures. To overcome the problems associated with resistance of small via structures, it is common to either provide elongate via structures, which are essentially elongated rectangles in cross-section which pass between the chosen layers, or larger filled vias which have an increased two dimensional cross-sectional area, i.e. large area squares. In both of these cases, the increased volume of the via improves the resistive heating effects.
Unfortunately, while elongate vias or larger surface area vias show improved resistance effects, the patterning and processing of such vias can be troublesome. In particular, long elongate vias can suffer from seam formation during metallization stages. During the deposition of the metal into the via structures, such metal will tend to grow inwards from the side walls of the via holes, and may form a seam at the center of the via. Additionally, the metal may form a complete layer at the top of the via prior to fully filling the via hole structure, which leads to voids running along the length of the elongate via. This degrades the resistance improvement effects of such a via, and can also lead to significant problems when surface planarization is required.
The larger two dimensional via structures, while in principle leading to high density and low resistance, suffer from inhomogeneities in the metal deposition, and furthermore during planarization such structures do not give fully planar top surfaces in line with the semiconductor substrate.